VTL Verification Engineer_SMTS_52555

Job description

During the current global health crisis, the priority for Siemens Digital Industries Software is the health and wellbeing of our entire community including current and future employees, which may add time to our hiring processes.  We appreciate your patience and invite you to visit our website to learn more about how Siemens is responding to the pandemic. 

Individual will be responsible for performing design verification for Transactors.

·  Primary responsibilities include understanding standard specifications, creating verification test plans and environments, testcase development, VIP usage, and the ability to debug of defects found through verification processes.
·  Applicant should have proficiency in object oriented programming using languages such as C++ and SystemVerilog,
·  Experience in scripting languages such as Perl, working knowledge of hardware description language (HDL) (VHDL or Verilog), computer architecture, experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc. , and demonstrated communication skills (written and oral).

Qualification:
·  (BE/BTech/ME/MTech/MS) From any of the premier engineering institues.Experience in any of the protocols like PCIe, Ethernet, MIPI, AMBA etc.
·  5-10 years experience in System Verilog/C++ / OOP Skills, VHDL/Verilog

Organization: Digital Industries

Company: Mentor Graphics (India) Private Limited

Experience Level: Experienced Professional

Job Type: Full-time