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  • Guadalajara (Guadalajara)
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Job description

Job Description

The Silicon Development team within the Data Center Group is responsible for designing and delivering future generations of Intel's high performance interconnect fabric components for large scale, cloud and enterprise customers. We have an opening for a Pre-Silicon Val/Design Intern on the next generation networking fabric ASIC design.

The activities for this position include, but are not limited to:

- Develop test plans and test strategies for logic blocks.

- Programming verification tests, test execution, triage and failure debug.

- Providing feedback to logic and design teams to improve the design during the pre-silicon design phase.

- Perform logic design, Register Transfer Level RTL coding, generate cell libraries, functional units, and sub-systems for inclusion in full chip designs.

- Identify and implement RTL bug and timing fixes to support verification and structural design teams.

- Continuous collaboration with other individuals, teams, and groups within Intel to maximize reuse of technology, as well as fostering innovation, thus adding to the continued engineering efficiency overall.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Desired profile

Qualifications

Candidate should be pursuing a Bachelor's or a Master's degree in Electronics Engineering or related field. The ideal candidate should exhibit:

- Good understanding of digital design, ASIC design flow and computer architecture

- Knowledge of at least one hardware description language. System Verilog is desired.

-Basic testbench development. OVM/UVM is highly desired.

- Good programming/scripting skills. Experience in Python/Perl is a plus.

- Experience with UNIX environments.

- Strong analytical ability, problem-solving and debugging skills.

- Good written and verbal communication.

- Disciplined, motivated and innovative, with a focus on quality.

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